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Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems /
Tag	Description
020	$a9789400904873$9978-94-009-0487-3
082	$a004.0151$223
099	$aOnline resource: Springer
245	$aSelf-Timed Control of Concurrent Processes$h[EBook] :$bThe Design of Aperiodic Logical Circuits in Computers and Discrete Systems /$cedited by Victor I. Varshavsky.
260	$aDordrecht :$bSpringer Netherlands,$c1990.
300	$a432 p.$bonline resource.
336	$atext$btxt$2rdacontent
337	$acomputer$bc$2rdamedia
338	$aonline resource$bcr$2rdacarrier
440	$aMathematics and Its Applications (Soviet Series),$x0169-6378 ;$v52
505	$a1 Introduction -- 2 Asynchronous processes and their interpretation -- 2.1 Asynchronous processes -- 2.2 Petri nets -- 2.3 Signal graphs -- 2.4 The Muller model -- 2.5 Parallel asynchronous flow charts -- 2.6 Asynchronous state machines -- 2.7 Reference notations -- 3 Self-synchronizing codes -- 3.1 Preliminary definitions -- 3.2 Direct-transition codes -- 3.3 Two-phase codes -- 3.4 Double-rail code -- 3.5 Code with identifier -- 3.6 Optimally balanced code -- 3.7 On the code redundancy -- 3.8 Differential encoding -- 3.9 Reference notations -- 4 Aperiodic circuits -- 4.1 Two-phase implementation of finite state machine -- 4.2 Completion indicators and checkers -- 4.3 Synthesis of combinatorial circuits -- 4.4 Aperiodic flip-flops -- 4.5 Canonical aperiodic implementations of finite state machines -- 4.6 Implementation with multiple phase signals -- 4.7 Implementation with direct transitions -- 4.8 On the definition of an aperiodic state machine -- 4.9 Reference notations -- 5 Circuit modelling of control flow -- 5.1 The modelling of Petri nets -- 5.2 The modelling of parallel asynchronous flow charts -- 5.3 Functional completeness and synthesis of semi-modular circuits -- 5.4 Synthesis of semi-modular circuits in limited bases -- 5.5 Modelling pipeline processes -- 5.6 Reference notations -- 6 Composition of asynchronous processes and circuits -- 6.1 Composition of asynchronous processes -- 6.2 Composition of aperiodic circuits -- 6.3 Algebra of asynchronous circuits -- 6.4 Reference notations -- 7 The matching of asynchronous processes and interface organization -- 7.1 Matched asynchronous processes -- 7.2 Protocol -- 7.3 The matching asynchronous process -- 7.4 The T2 interface -- 7.5 Asynchronous interface organization -- 7.6 Reference notations -- 8 Analysis of asynchronous circuits and processes -- 8.1 The reachability analysis -- 8.2 The classification analysis -- 8.3 The set of operational states -- 8.4 The effect of non-zero wire delays -- 8.5 Circuit Petri nets -- 8.6 On the complexity of analysis algorithms -- 8.7 Reference notations -- 9 Anomalous behaviour of logical circuits and the arbitration problem -- 9.1 Arbiters -- 9.2 Oscillatory anomaly -- 9.3 Meta-stability anomaly -- 9.4 Designing correctly-operating arbiters -- 9.5 “Bounded” arbiters and safe inertial delays -- 9.6 Reference notations -- 10 Fault diagnosis and self-repair in aperiodic circuits -- 10.1 Totally self-checking combinational circuits -- 10.2 Totally self-checking sequential machines -- 10.3 Fault detection in autonomous circuits -- 10.4 Self-repair organization for aperiodic circuits -- 10.5 Reference notations -- 11 Typical examples of aperiodic design modules -- 11.1 The JK-flip-flop -- 11.2 Registers -- 11.3 Pipeline registers -- 11.4 Converting single-rail signals into double-rail ones -- 11.5 Counters -- 11.6 Reference notations -- Editor’s Epilogue -- References.
538	$aOnline access to this digital book is restricted to subscription institutions through IP address (only for SISSA internal users)
700	$aVarshavsky, Victor I.$eeditor.
710	$aSpringerLink (Online service)
830	$aMathematics and Its Applications (Soviet Series),$x0169-6378 ;$v52
856	$uhttp://dx.doi.org/10.1007/978-94-009-0487-3